/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef DEVDRV_PLATFORM_RESOURCE_H
#define DEVDRV_PLATFORM_RESOURCE_H

#include "devdrv_user_common.h"
#include "tsdrv_kernel_common.h"

#ifdef TSDRV_UT
#define DEVDRV_TS_BINARY_PATH DTB_FILE_NAME
#else
#define DEVDRV_TS_BINARY_PATH "/var/tsch_fw.bin"
#endif
#define DEVDRV_AICPU_BINARY_PATH "/var/aicpu_fw.bin"

#define DEVDRV_SCLID 2
#define DEVDRV_CCPU_CLUSTER 0
#define DEVDRV_AICPU_CLUSTER 0
#define DEVDRV_TSCPU_CLUSTER 1

/* all CPU numbers, including control CPU */
#define AICPU_MAX_NUM 16
#define CONFIG_CORE_PER_CLUSTER 0x8
#define CONFIG_CLUSTER_PER_TOTEM 0x1

/* *************** aicpu config *************** */
#define FW_CPU_ID_BASW_OF_FPGA 2
#define FW_CPU_NUM_OF_FPGA 2
#define FW_CPU_ID_BASW 4
#define FW_CPU_NUM 4

#define DEVDRV_MAILBOX_SEND_OFFLINE_IRQ 1
#if defined(CFG_SOC_PLATFORM_MINIV3) && !defined(CFG_SOC_PLATFORM_MINIV2)
#define DEVDRV_CQ_PER_IRQ 32
#define DEVDRV_CQ_IRQ_NUM 16
#else
#define DEVDRV_CQ_PER_IRQ 16
#define DEVDRV_CQ_IRQ_NUM 32
#endif

#define CPU_TYPE_OF_CCPU 0
#define CPU_TYPE_OF_TS 1
#define CPU_TYPE_OF_AICPU 2
#define CPU_TYPE_OF_DCPU 3
#define DEVDRV_TS_MEMORY_SIZE (184 * 1024 * 1024)
#define DEVDRV_TS_DOORBELL_SIZE (DEVDRV_TS_DOORBELL_NUM * DEVDRV_TS_DOORBELL_STRIDE)

enum devdrv_dts_addr_index {
    DEVDRV_DTS_GIC_BASE_INDEX = 0,
    DEVDRV_DTS_DISPATCH_INDEX = 1,
    DEVDRV_DTS_SYSCTL_INDEX = 2,
#ifdef CFG_SOC_PLATFORM_MINIV3
    DEVDRV_DTS_STARS_INDEX,
    DEVDRV_DTS_ARM_RAS_INDEX,
    DEVDRV_DTS_MAX_RESOURCE_NODE
#else /* CFG_SOC_PLATFORM_MINIV3 */
    DEVDRV_DTS_MAX_RESOURCE_NODE = 8
#endif /* CFG_SOC_PLATFORM_MINIV3 */
};

struct devdrv_ts_pdata {
    u32 tsid;

    void __iomem *sram_vaddr;
    u8 __iomem *ts_mbox_send_vaddr;
    u8 __iomem *ts_mbox_rcv_vaddr;
    u32 __iomem *ts_sysctl_vaddr;
    void __iomem *doorbell_vaddr;
    void __iomem *stars_ctrl_vaddr;

    u64 sram_paddr;
    u64 ts_mbox_send_paddr;
    u64 ts_mbox_rcv_paddr;
    u64 doorbell_paddr;
    u64 ts_sysctl_paddr;
    u64 stars_ctrl_paddr;

    size_t sram_size;
    size_t ts_mbox_send_size;
    size_t ts_mbox_rcv_size;
    size_t doorbell_size;
    size_t ts_sysctl_size;
    size_t stars_ctrl_size;

    u16 irq_cq_update[DEVDRV_CQ_IRQ_NUM];
    u16 irq_cq_update_request[DEVDRV_CQ_IRQ_NUM];
    int irq_mailbox_ack;
    int irq_mailbox_ack_request;
    int irq_mailbox_data_ack;
    int irq_mailbox_data_ack_request;
    int irq_functional_cq;
    int irq_functional_cq_request;
    int disp_nfe_irq;

    u64 ts_sq_static_addr;
    size_t ts_sq_static_size;

    u8 ts_start_fail;
    int ts_load_fail;

    dma_addr_t ts_dma_handle;
    void *ts_load_addr;

    u32 ts_cpu_core_num;
};

struct devdrv_platform_info {
    u32 board_id;
    u32 slot_id;

    u32 occupy_bitmap;

    void __iomem *gicv3_base;
    void __iomem *sysctl_base;
    void __iomem *disp_base;

    u32 sclid;
    u32 ts_cluster;
    u32 ccpu_cluster;
    u32 aicpu_cluster;

    u64 devdrv_addr_base[DEVDRV_DTS_MAX_RESOURCE_NODE];
};

struct devdrv_platform_data {
    u32 dev_id;
    u32 env_type;
    u32 ts_mem_restrict_valid;
    u32 ai_core_num;
    u32 ai_core_freq;
    u64 ai_core_bitmap;
    union {
        struct devdrv_pci_info pci_info;
        struct devdrv_platform_info platform_info;
    };

    u32 ts_num; /* actual ts number for this platform */
    struct devdrv_ts_pdata ts_pdata[DEVDRV_MAX_TS_NUM];
    u32 vector_core_num;
    u32 vector_core_freq;
    u64 vector_core_bitmap;
    u8 ai_core_num_level; /* 0 invalid */
    u8 ai_core_freq_level; /* 0 invalid */
};

enum dev_chip_id {
    CHIP0_ID,
    CHIP1_ID,
    MAX_CHIP_NUM
};

#endif /* __DEVDRV_PLATFORM_RESOURCE_H */
